Caption and photo are from a Raytheon document, courtesy of From Die photo of the dual 3-input NOR gate used in the AGC. It also provides another incentive to make the software error free." It helps that Frank O’ Brien (of AGC fame) is a guest speaker there on a regular basis. We are currently investigating options to deal with this.

"So it's got to be rugged. These voltages are produced by voltage regulators on the sense amplifier modules that use Zener diodes for regulation. As a graduate student, he worked with the MIT team that developed the AGC. (This circuit is rather confusing; you might expect the circuit to be a loop through the sense wire and the sense amplifier transformer, NASA discovered in early testing that wires could be sheared inside the module, due to vibrations between The memory cores and the switching core were physically very different. The AGC's logic circuitry (including the processor) was implemented with NOR gates. The Y select signals were similar, using an 8×10 matrix. However, we're thinking of changing the wiring so the parity bit replaces the bad bit, and then we just disable parity checking. The obvious approaches would be to use four set lines (one per plane), or one set line (and use reset to block the others). outputs are numbered starting at 1 (1AXBF-8AXBF). As a result, the Block I rope modules had a different shape: roughly square in cross-section, unlike the flat Block II modules.

Eight sense amplifiers are visible and eight other sense amplifiers are on the other

Reversing the polarity of the drivers reverses the current flow, and energizing different drivers selects a different line. The RAM had one sense amp module with 16 amplifiers in slot B13, It also used numerous analog circuits built from discrete components using unusual cordwood construction.By removing the bolts holding the two trays together, we could disassemble the AGC. Two women passed a needle back and forth through the cores to create this wiring. requiring a new core rope to be manufactured every time. In addition to the core memory module itself, the AGC required several modules of supporting circuitry. In general, the AGC's logic circuits weren't cleanly partitioned across modules since making everything fit was more important than a nice design. Core rope memory is a form of read-only memory (ROM) for computers, first used in the 1960s by early NASA Mars space probes and then in the Apollo Guidance Computer (AGC) designed and programmed by the Massachusetts Institute of Technology (MIT) Instrumentation Lab and built by Raytheon. Several registers could be read onto the read bus simultaneously. Block I was used during the uncrewed The decision to expand the memory and instruction set for Block II, but to retain the Block I's restrictive three-bit op. Early modules (including ours) were susceptible to wire breakages from vibrations. This was similar to reset, but was needed due to a complexity of the AGC's opcode decoding. But if the core was in the 0 state to start, the sense line wouldn't pick up a voltage. Because the system used odd parity, at most 15 of the 16 bits can be high. The cores were encased (potted) in protective epoxy to protect them during flight, so the cores are not visible.Wiring of the core rope was a tedious process that The sense amplifiers required carefully-tuned voltage levels for bias and thresholds so The Uprupt interrupt was triggered after its counter, executing the Shinc subsequence, had shifted 16 bits of uplink data into the AGC.

Photo: Mark Richards/Computer History Museum A prototype of the rope memory used in the Apollo Guidance Computer. density improvement over the planned core-transistor logic, making the AGC possible.